1. Field of the Invention
The present invention relates to output drivers and, more particularly, to an output driver with split pins.
2. Description of the Related Art
A high-voltage driver is an electronic circuit that is used in a number of applications. For example, large transistors, which handle hundreds of volts, can be turned on and off with high-voltage drivers. In addition, DC-to-DC converters, such as buck and boost converters, can use high-voltage drivers to provide a switched current source.
FIG. 1 shows a cross-sectional diagram that illustrates a prior-art high-voltage driver 100. As shown in FIG. 1, driver 100 is formed in a semiconductor structure 110 that includes a p-type substrate 112, along with an n− well 114 and a p− well 116 that are formed in p-type substrate 112.
In addition, semiconductor structure 110 includes an n+ contact region 118 that is formed in n− well 114, and a p+ contact region 120 that is formed in p− well 116. N+ contact region 118 is electrically connected to a power line 122 to place a power supply voltage on n− well 114, while p+ contact region 120 is electrically connected to a ground line 124 to place ground on p− well 116. Further, semiconductor structure 110 includes a shallow trench isolation region STI that isolates n− well 114 from p− well 116.
As also shown in FIG. 1, driver 100 includes a PMOS transistor 126 and an NMOS transistor 128. PMOS transistor 126 includes spaced-apart p+ source and drain regions 130 and 132 that are formed in n− well 114, and a channel region 134 that lies between and contacts the source and drain regions 130 and 132. PMOS transistor 126 also includes a layer of gate oxide 136 that contacts the top surface of n− well 114, and a gate 138 that contacts oxide layer 136 and lies over channel region 134.
NMOS transistor 128, in turn, includes spaced-apart n+ source and drain regions 140 and 142 that are formed in p− well 116, and a channel region 144 that lies between and contacts the source and drain regions 140 and 142. NMOS transistor 128 also includes a layer of gate oxide 146 that contacts the top surface of p− well 116, and a gate 148 that contacts oxide layer 146 and lies over channel region 144.
In addition, p+ drain region 132 and n+ drain region 142 are electrically connected together and to an output pin 150. Further, p+ source region 130 is electrically connected to power line 122 to place the power supply voltage on p+ source region 130, while n+ source region 140 is electrically connected to ground line 124 to place ground on source region 140.
In operation, when the voltage on the gates 138 and 148 of transistors 126 and 128 goes high, PMOS transistor 126 turns off while NMOS transistor 128 turns on to sink a current from output pin 150, thereby pulling the voltage on output pin 150 down. On the other hand, when the voltage on the gates 138 and 148 of transistors 126 and 128 goes low, NMOS transistor 128 turns off, while PMOS transistor 126 turns on to source a current to output pin 150, thereby pulling the voltage on output pin 150 up.
One limitation of driver 100 is that driver 100 is susceptible to an electrostatic discharge (ESD) pulse. An ESD pulse, which can occur when a chip is handled prior to being attached to a printed circuit board, momentarily places a very high potential on a pin while the chip is otherwise powered off. If another pin is grounded, a very large current can flow from the high potential pin through circuitry in the chip to the grounded pin. If the pins are not ESD protected, the current can destroy the circuitry in the chip.
Thus, prior to an ESD event, all of the nodes of driver 100 are equal to ground. However, when an ESD event occurs on output pin 150 with respect to pin 124, the voltage on output pin 150 spikes up quickly. This, in turn, causes the voltage on the drain regions 132 and 142 to spike up quickly. When the voltage on drain region 132 spikes up, a parasitic pn diode 152, which is formed from p+ drain region 132 and n− well 114/n+ contact region 118, responds to spike.
Since all of the other nodes of transistor 126 are at ground, the diode becomes forward biased when the voltage on drain region 132 reaches approximately 0.7V. As a result, the voltage on power line 122 spikes up and follows the quickly rising voltage on p+ drain region 132 with a voltage that is approximately 0.7V less than the voltage on p+ drain region 132.
When the voltage on power line 122 spikes up, the voltage on the gates 138 and 148 of the transistors 126 and 128 is quickly pulled up due to a capacitive coupling between power line 122 and the gates 138 and 148. As a result, PMOS transistor 126 turns off, while NMOS transistor 128 turns on and begins to sink an ESD current from drain region 142 and output pin 150 to ground line 124.
However, even though NMOS transistor 128 turns on and sinks the ESD current, the power density is often too great for transistor 128. As a result, the ESD current flowing through NMOS transistor 128 can overheat and destroy NMOS transistor 128. Thus, an ESD event on output pin 150 can lead to the destruction of NMOS transistor 128.
One common approach to providing ESD protection is to connect an ESD clamp, such as a grounded-gate NMOS transistor, between an output pin and ground. To provide ESD protection, a grounded-gate NMOS must provide an open circuit between the output pin and ground during normal operation, and only provide an ESD current path between the output pin and ground when the voltage on the output pin spikes up to a value which is greater than the maximum voltage that can be present during normal operation plus a margin voltage. A grounded-gate NMOS transistor, however, can not provide the needed protection in this situation.
FIG. 2 shows a graph that illustrates an example of the safe operating area of NMOS transistor 128. As shown in FIG. 2, when the gate-to-source voltage is near zero, transistor 128 can handle a drain-to-source voltage of approximately 130V. On the other hand, when the gate-to-source voltage is approximately 7V, transistor 128 can only handle a drain-to-source voltage of approximately 65V. A voltage that is greater than 65V places transistor 128 in the failure area.
Thus, if transistor 128 is designed to handle, for example, 100V when the gate-to-source voltage is near zero, a grounded-gate NMOS transistor can only turn on when n+ drain region 142 reaches 100V plus a margin voltage of, for example 5V, for a total voltage of 105V. If the grounded-gate NMOS transistor turns on at any voltage less than 100V, the grounded-gate NMOS transistor will turn on during normal operation, thereby preventing transistor 128 from operating as intended.
However, since the gate-to-source voltage of transistor 128 quickly follows the voltage spike on drain region 142, the gate-to-source voltage of transistor 128 will reach 7V before the drain-to-source voltage of transistor 128 can exceed 100V. Thus, as shown in FIG. 2, transistor 128 will reach a destructive point before the grounded-gate NMOS transistor can turn on. As a result, there is a need for a circuit that allows a high-voltage driver to be ESD protected.